1. Field of the Invention
This invention relates in general to power amplifiers and, in particular, to power amplifier modules. More specifically, but without restriction to the particular embodiments hereinafter described in accordance with the best mode of practice, this invention relates to power amplifier modules for use in wireless communications and includes related systems, devices, and methods.
2. Description of Related Technology
Power amplifiers can be included in mobile devices to amplify a RF signal for transmission via an antenna. For example, in mobile devices having a time division multiple access (TDMA) architecture, such as those found in Global System for Mobile Communications (GSM), code division multiple access (CDMA), and wideband code division multiple access (W-CDMA) systems, a power amplifier can be used to amplify a RF signal having a relatively low power. It can be important to manage the amplification of a RF signal, as a desired transmit power level can depend on how far the user is away from a base station and/or the mobile environment. Power amplifiers can also be employed to aid in regulating the power level of the RF signal over time, so as to prevent signal interference from transmission during an assigned receive time slot.
The power consumption of a power amplifier and power added efficiency (PAE) associated therewith can be an important consideration. In view of the ever increasing demands associated with providing wireless communication for voice, data, and system control, there is a need for improved power amplifiers, power amplifiers modules, and devices, systems, and methods relating thereto. Furthermore, there is a need for power amplifiers having improved power efficiency.
Certain specific aspects of the present invention relate to the field of integrated circuit packaging, and more particularly to systems and methods of forming wire bond pads for packaging radio frequency (RF) integrated circuits (ICs).
Silicon or other semiconductor wafers are fabricated into integrated circuits as is known to one of ordinary skill in the art of IC fabrication. An IC is bonded and electrically connected to a carrier or substrate, which has layers of dielectric and metal traces, and packaged for use. A surface plating material is plated onto the top layer of copper traces to provide electrical connection points between the IC and the substrate, permitting the IC to interface with the outside world. Traditionally, nickel/gold (Ni/Au) has been a standard surface plating material for RFIC products and in certain situations, the RFIC is wire-bonded to the Ni/Au wire-bond pads plated on the surface of the substrate to form the electrical connections of the RFIC with its package. However, increases in gold prices have increased packaging costs associated with the Ni/Au surface plating.
Other particular aspects of the present invention relate to the field of integrated circuit layout and packaging, and more particularly to systems and methods of layout and packaging of radio frequency (RF) integrated circuits (ICs).
Still other aspects of this invention more particularly to bipolar transistors and products that include bipolar transistors. Bipolar transistors, such as heterojunction bipolar transistors (HBTs), are implemented in a wide variety of applications. Such bipolar transistors can be formed on semiconductor substrates, such as gallium arsenide (GaAs) substrates. One illustrative application for a bipolar transistor is in a power amplifier system. As technology evolves, specifications for power amplifier systems have become more demanding to meet.
As indicated above, one aspect of power amplifier performance is linearity. Measures of linearity performance can include channel power ratios, such as the adjacent channel power ratio (ACPR1) and the alternative channel power ratio (ACPR2), and/or channel leakage power ratios, such as an adjacent channel leakage power ratio (ACLR1) and an alternative channel leakage power ratio (ACLR2). ACPR2 and ACLR2 can be referred to as second channel linearity measures. ACPR2 and ACLR2 values can correspond at measurements at an offset of about 1.98 MHz from a frequency of interest.
Conventionally, most publications in the literature have focused on ACPR1 and ACLR1 linearity measures and little has been published about ACRP2 or ACLR2. Recent ACPR2 and ACLR2 system specifications from industry have been particularly difficult to meet, especially while meeting other system specifications related to RF gain. Accordingly, a need exists for improved linearity in systems that include bipolar transistors, such as power amplifier systems.
Yet still further aspects of the present disclosure relate to a dual mode digital control interface for power amplifiers.
A number of electronic devices, including wireless devices, may have one or more components that are controlled or set by a front-end component. For example, a power amplifier may be set or configured by a power amplifier controller. In some cases, the power amplifier controller may itself be controlled or configured by another interface component based on the state of the device.
Often, various components within a device will be created by different organizations. To facilitate interoperability between components, which may be designed by different organizations, standards are often adopted for different types of devices and components. As technology advances, standards may change or new standards may be adopted. In some cases, the newer standards are not compatible with the older standards.
And still yet other aspects of the present invention relate to heterojunction bipolar transistor (HBT) power amplifier bias circuits. Power amplifiers are typically active elements that can magnify an input signal to yield an output signal that is significantly larger than the input signal. Many types of power amplifiers exist and there are many ways to create power amplifiers. For example, some power amplifiers can be created using heterojunction bipolar transistors (HBT). Many HBT power amplifiers use a diode stack bias configuration. In some such configurations, the diode stack bias configuration exhibits sensitivity to the device beta, which can result in substantial quiescent current variation of the amplifier. Further, the variation of quiescent current may impact performance parameters and may degrade product yield.
Further aspects hereof relate to the understanding that in some semiconductor material systems it is possible to combine different device technologies on a single semiconductor die to form hybrid structures. For example, in certain material systems, it is possible to integrate a heterojunction bipolar transistor (HBT) with a field effect transistors (FET) on a single substrate, to fabricate what is referred to as a BiFET. Devices, such as RF power amplifiers, can be fabricated using BiFET technology to have increased design flexibility. As a result, a BiFET power amplifier including an HBT and a FET can be advantageously designed to operate at a lower reference voltage than a bipolar transistor power amplifier. Of particular interest to device manufacturers are high power BiFET amplifiers, which can be formed by integrating a FET into a gallium arsenide (GaAs) HBT process. However, previous attempts to integrate a FET into a GaAs HBT process have resulted only in an n-type FET device.
Therefore, it would be desirable to have a BiFET device structure that includes a p-type FET device, and that may include complementary n-type and p-type FET devices.
And yet still other aspects of the improved technology disclosed herein relate to terminating a harmonic component of a signal. In relatively high frequency applications, such as radio frequency (RF) applications, unwanted signal reflection and/or noise can occur. Such unwanted signal reflection and/or noise can occur at a fundamental frequency of the signal and/or other frequencies, such as harmonics of the fundamental frequency of the signal. To reduce the impact of signal reflection and/or noise, impedance matching can be implemented. One illustrative application in which it is advantageous to minimize unwanted signal reflection and/or noise is a power amplifier system.
Power added efficiency (PAE) is one metric for rating power amplifiers. In addition, linearity is another metric for rating power amplifiers. PAE and/or linearity can be metrics by which customers, such as original equipment manufacturers (OEMs), determine which power amplifiers to purchase. For instance, power amplifiers with a PAE below a certain level may not be purchased by a customer due to the impact of PAE on the customer's product. A lower PAE can, for example, reduce the battery life of an electronic device, such as a mobile phone. However, enhancing PAE can come at the cost of adversely impacting linearity. Similarly, improving linearity can cause a decrease in PAE. At the same time, customers want power amplifiers with high linearity and high PAE.
A load line at an output of a power amplifier can impact both PAE and linearity. Some conventional power amplifier systems have included a load line to match an impedance of the power amplifier output at a fundamental frequency of the power amplifier output signal and also to perform harmonic termination. However, it has proved difficult to match an impedance of the fundamental frequency of the power amplifier output while including harmonic termination in a way that optimizes both PAE and linearity. Accordingly, a need exists to improve both linearity and PAE of a power amplifier.
Now still further aspects of the present invention relate to transmission lines for high performance radio frequency applications.
Transmission lines can be implemented in a variety of contexts, such as on a packaging substrate or printed circuit board (PCB). Multi-layer laminate PCBs or package substrates are extensively used in radio frequency (RF) applications.
RF circuits, such as power amplifiers, low noise amplifiers (LNAs), mixers, voltage controlled oscillators (VCOs), filters, switches and whole transceivers have been implemented using semiconductor technologies. However, in RF modules (for example, an RF front-end module including power amplifiers, switches, and/or filters), single chip integration may not be practical due to different blocks being implemented in different semiconductor technologies. For instance, a power amplifier may be formed by a GaAs process, while related control and/or bias circuitry may be formed by a CMOS process.
Long transmission lines and/or other on chip passives can consume large chip area. Consequently, multi-chip module (MCM) and/or system in package (SiP) assembly technology can be used to achieve low cost, small size and/or high performance in RF modules. Laminate technology can be used for MCM assembly, in which transmission lines are implemented on a laminate substrate. Conductor loss in such transmission lines can have a significant impact on the performance of any of the elements in the MCM. Accordingly, laminate plating technology can impact RF performance significantly.
The cost of laminate technology can be driven by the choice materials for performance and/or assembly needs. RF SiPs that use gold (Au) wire bonding to connect RF circuit elements to transmission lines can use a variety of different finish platings such as lower loss, more expensive NiAu (for example, due to thicker Au) or higher loss, less expensive NiPdAu. Accordingly, a need exists for cost effective, high performance technology for RF transmission lines.
And yet further aspects related to apparatus and methods for tantalum nitride terminated through-wafer vias. In certain implementations, a tantalum nitride (TaN) termination layer is formed on a first or front side of a gallium arsenide (GaAs) wafer, and a gold conductive layer is formed over the TaN termination layer. Thereafter, a through-wafer via is etched into a second or back side of the GaAs wafer so as to extend through the GaAs wafer and a first or inner portion of the TaN termination layer to reach the gold conductive layer. In certain implementations, the through wafer via is plated with a nickel vanadium (NiV) barrier layer, a gold seed layer, and a copper layer. During through-wafer via formation, a second or outer portion of the TaN termination layer is maintained and configured to surround an interface between the gold conductive layer and the copper layer so as to inhibit diffusion of copper into the GaAs wafer.
TaN terminated through-wafer vias can provide improved metal adhesion and reduced copper migration relative to schemes employing silicon nitride termination and a sputtered barrier layer. Furthermore, in certain implementations using a TaN termination layer to terminate a through-wafer via can permit the location or position of the through wafer via to be moved without changing fabrication or lithographical masks associated with transistor structures formed on the front side of the GaAs wafer. Configuring the through-wafer vias to be movable without changing lithographical mask associated with transistors can increase design flexibility and/or reduce time and cost associated with incremental fixes or tape-outs of integrated circuits designs that include the through-wafer vias.
In addition to the above, still further aspects of the present disclosure relate to packaged semiconductor structures and, more particularly, to structures that provide radio frequency (RF) isolation and/or electromagnetic radiation.
Packaged semiconductor components can include integrated shielding technology within a package. To form a shield, which can be referred to as a “Faraday cage,” a top layer conductive layer can be electrically connected to a bottom conductive layer by vias. For instance, the bottom conductive layer can be a ground plane and the vias can connect the top conductive layer to ground. The vias can provide an electrical connection between the top and the bottom conductive layers and also function as part of the shield itself. However, the vias can consume a significant amount of area in the package. At the same time, the vias can affect a strength of the ground connection of the shield.
Further to the above, additional aspects of this invention are directed to semiconductor device packages and, more particularly, to electromagnetic and/or radio frequency interference shielding for semiconductor devices.
There exists a general need in radio frequency (RF) communication systems for RF devices to be isolated from electromagnetic (radio frequency) interference (EMI) generated by other RF devices in order to maintain proper device performance. Similarly, the RF devices generally need to be isolated from the electromagnetic interference received from, or transmitted to, the environment.
The traditional method of isolating RF devices from such electromagnetic interference is to cover the RF device with a grounded metal enclosure typically called a “can.” However, this solution is costly and lacks design flexibility. In addition, the metal can adds significant size to the device footprint on a printed circuit board, and also adds weight to the printed circuit board.
Implementing one or more of the features, attributes, or characteristics described in further detail in the various following sections hereof can achieve desirable linearity and PAE in a power amplifier system. Moreover, implementing in a power amplifier system one or more features described in the following disclosure can achieve desirable FOM and/or other metrics by which power amplifiers are rated. Although some features hereof are described in connection with a power amplifier module for illustrative purposes, it will be understood by those of skill in the art that the principles and advantages described herein can be applied to other portions of a power amplifier system, such as in a power amplifier die, a substrate for use with a power amplifier die, and a wireless communications device that includes a power amplifier, and in any and all other applications that would be apparent to those skilled in any analogous art.